A 750-nW 1-MHz 9-tap analog finite impulse response filter for wireless senor network chip

This paper presents a low power Finite Impulse Response (FIR) filter based on discrete-time analog computing. The analog FIR filter is first presented to deal with analog signal. To improve linearity, two-double boost technique is introduced in the sample and hold cells which are used to achieve delay-time function. Meanwhile, the four-quadrant voltage-mode multiplier consists of PMOS substract cell and combiner cell, which is independent of device parameters. To realize the shift registers function, the rotating switch matrix circuit is adopted controlled by phase shift clocks. All MOS transistors implemented in this architecture are biased in subthreshold region with a supply voltage of 0.6 V to reduce the power consumption. Simulation results show that the analog FIR filter dissipates 750 nW at 1 MHz sample frequency and the effective number of bits of the proposed analog FIR filter is more than 7 bits. Compared to the conventional digital FIR filter, power consumption is reduced by 72.22% at 1 MHz in a 0.18μm CMOS process.