Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor

A output capacitor-free low-dropout regulator (LDO) with fast transient response and ultra-small compensation capacitor is proposed. The slew-rate enhancement (SRE) circuit based on dynamic biasing technique is designed to improve load transient response for 100 mA load step. The SRE circuit structure does not use any passive element to save silicon area and cost. The total active area of the proposed LDO is 0.043 mm2 with 0.4 pF on-chip compensation capacitor and the stability analysis is also included. The proposed LDO is implemented in 0.35 µm process and experimental results show that it regulates the output voltage at 1.8 V and 1 V with dropout voltage of 200 mV, 100 mA maximum output-load current. The measured quiescent current is 15 μA only. For a 2 V input voltage, the proposed LDO is able to regulate output voltage of 1.8 V within 2 μs with less than 148 mV overshoot and undershoot. For a 1.2 V input voltage, the LDO is able to regulate output voltage of 1 V within 3 μs with less than 152 mV overshoot and undershoot.