Network topology design

The application of Industrial Ethernet brings up issues of reliability and behaviour of the networks under a demanded load, while preserving the permitted time delay in the whole network. An algorithm that designs network topology, which meets the required fault tolerance and allows reliable communication between parts of the control system is proposed. It is an iterative genetic algorithm designing the physical topology and verifying the behaviour under the expected load and time delay in the whole network. It is necessary to propose chromosome representation and required genetic operators as well. The results of the proposed algorithm show that it is suitable especially for the design of control network topologies, which has been its main aim. According to the authors' knowledge there are no other algorithms fulfilling the requirements to such an extent as the proposed algorithm does.

► The designed network has different fault tolerance in different parts of the network.
► The solution found always meets the demands for fault tolerance.
► It is easy to enhance the algorithm for different limitations such as limited node degree etc.