Programmable logic design of a compact Genetic Algorithm for phasor estimation in real-time

• The paper presents a novel application of Genetic Algorithms in PMU development.
• The proposed method presents the frequency estimation, as well as the amplitude and phase.
• The efficiency of a compact Genetic Algorithms for phasor estimation is highlighted.
• The accuracy of the method presents a faster recovering time in transient situations if compared to conventional methods.
• A complete power system was simulated for testing purposes and the proposed technique was implemented in hardware (FPGA).

The main objective of this work is to present an efficient method for phasor estimation based on a compact Genetic Algorithm (cGA) implemented in Field Programmable Gate Array (FPGA). To validate the proposed method, an Electrical Power System (EPS) simulated by the Alternative Transients Program (ATP) provides data to be used by the cGA. This data is as close as possible to the actual data provided by the EPS. Real life situations such as islanding, sudden load increase and permanent faults were considered. The implementation aims to take advantage of the inherent parallelism in Genetic Algorithms in a compact and optimized way, making them an attractive option for practical applications in real-time estimations concerning Phasor Measurement Units (PMUs).