Single and three phase moving average filter PLLs: Digital controller design recipe

• This paper presents a simple controller design method for a PLL with moving average filter.
• Adequate design of a PLL with simple structure can present outstanding performance.
• PLL settling times are faster than the ones presented in literature.
• This PLL provides high attenuation for the grid harmonics.
• The variable moving average window version of the proposed PLL quickly tracks grid frequency variations.

This work proposes a simple and easy to use design recipe for the proportional–integral digital controller of a Phase Locked Loop using moving average filter and multiplier type phase detector. Based on fast controllers predesigned in this paper for the most common situations (50/60 Hz grid frequency, single and three-phase systems, presence of odd and/or even harmonics) the new proportional–integral controller parameters are obtained using analytical formulas for new operation conditions (input amplitude and sampling frequency). The new controller parameters obtained using this method avoids trial and error procedures and keeps the same PLL transient and steady state performance of the original design. Simulation and experimental results validate the proposed design recipe. Comparison with recent results in the literature confirms that the proposed design recipe method provides faster transient response and good steady state performance.