Improvement of cell reliability by floating gate implantation on 1Xnm NAND flash memory

Continuous scaling down NAND flash memory toward below 1Xnm node generation will result in serious floating gate (FG) poly depletion and significantly impact the cell reliability performance. In this study, the FG implantation before inter-poly-dielectric deposition was proposed. We have successfully explored the methods to minimize the FG implanted damage issue and hence the void-free control gate (CG) can be achieved after the CG poly-Si fill-in. After optimizing the FG implanted processes, the cell reliabilities on 1Xnm NAND flash device were verified. The FG poly depletion can be effectively reduced by the additional FG dopant, which results in the significant improvement on the natural threshold-voltage (Vt) distribution width, the program noise, and the program/erase Vt degradation. Moreover, there is no degradation on non-cycle data retention when adding the FG implantation, which suggests no extra FG dopant penetrated into tunnel oxide as the trap sites to enhance the trap-assisted tunneling leakage under high temperature baking.