On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

This paper demonstrates the improvement of DC analog performance of FD SOI transistors provided by the adoption of asymmetric self-cascode (A-SC) configuration. It consists of two transistors connected in series with gates shortened, acting as a single device. The doping concentration of the two transistors in the structure is different, leading to higher threshold voltage of the transistor at the source side of the composite structure than that of the transistor at the drain side. By reducing the doping concentration level at the channel of the transistor at drain side of the composite structure, forcing it to work in saturation, part of the applied drain bias is absorbed and does not reach the transistor close to the source, which is the main responsible for the overall device characteristics. As a result, larger drain current level and transconductance are obtained in comparison to symmetric self-cascode (where both transistors present same doping level) apart from promoting output conductance reduction. The transconductance, output conductance, Early voltage, and intrinsic voltage gain are used as figures of merit to demonstrate and validate the advantages of the proposed structure. The influence of channel length and doping concentration are also evaluated. The A-SC configuration is fully compatible with any standard FD SOI MOSFET technology with multiple threshold voltages. A simulation analysis demonstrates the feasibility of the proposed asymmetric structure in a UTBB FD SOI technology.