Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.