Comprehensive behavioral model of dual-gate high voltage JFET and pinch resistor

• Complex dual gate JFET behavioral model has been developed.
• Pinch-off voltage width scalability has been improved.
• Gate capacitance pinching effect for both independent gates has been implemented.
• Parasitic impact ionization current for both independent gates has been implemented.
• Statistical parameters simulating process distribution have been implemented.

Many analog technologies operate in large voltage range and therefore include at least one or more high voltage devices built from low doped layers. Such devices exhibit effects not covered by standard compact models, namely pinching (depletion) effects, in high voltage FETs often called quasisaturation. For example, the conventional compact JFET model is insufficient and oversimplified. Its scalability is controlled by the area factor, which only multiplies currents and capacitances but does not take into account existing 3-D effects. Also the optional second independent gate is missing. Therefore, the customized four terminal (4T) model written in Verilog-A (FitzPatrick and Miller, 2007; Sagdeo, 2007) was developed. It converges very well, its simulation speed is comparable with conventional compact models, and contains all required phenomena, including parasitic effects as, for example, impact ionization. This model has universal usage for many types of devices in various high voltage technologies such as stand-alone voltage dependent resistor, pinch resistor, drift area of power FET, part of special high side or start-up devices, and dual-gate JFET.