Design and optimization of impurity- and electrostatically-doped superlattice FETs to meet all the ITRS power targets at VDD = 0.4 V

• Full quantum simulation to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) SL-FETs.
• Sensitivity investigation to technological and design parameters.
• Relatively-low sensitivity to changes of most device parameters.
• Overall performances of an optimized ED SL-FET compared with ITRS road map requirements.
• ED InGaAs/InAlAs SL-FET a good candidate for the post-CMOS era.

In this work full-quantum simulations have been employed to devise and optimize both impurity-doped (ID) and electrostatically-doped (ED) superlattice FETs (SL-FETs). A sensitivity investigation to technological and design parameters has been carried out, showing a relatively-low sensitivity to changes of most device parameters. Results at a reduced power supply VDD=0.4V are compared with the ITRS specs projected to year 2022. Benchmarking highlights the potential of the proposed ED InGaAs/InAlAs SL-FET to perform up to 1.2× faster than HP specs with 5× lower energy-delay product. This device is thus expected to be a good candidate for the post-CMOS era.