Characterization and optimization of partially depleted SOI MOSFETs for high power RF switch applications

Power handling capability is the most stringent specification for an RF switch. The dominant reason to limit the power handling capability is undesirable channel formation (leakage current) on off-state FEETs in the event of large signal input. To characterize leakage current and find the correlation between DC I–V measurement and RF P1 dB measurement, a new DC characterization method (Float FET I–V characterization method) reflecting RF switch operation is proposed. Based on the proposed Float FET I–V method, an experimental study on optimum dc bias point, MOSFET device design, and stacked-FETs device design is performed in order to achieve maximum power handling capability of the RF switch. In addition, compared to RF measurement tests that take a long time, the proposed characterization method rapidly evaluates the various off-state MOSFET leakage current mechanisms affecting the power handling capability of the RF switch.

► The new DC characterization method is developed to find the correlation between DC I–V and RF P1 dB measurements.
► The proposed method rapidly evaluates various off-state MOSFET leakage current mechanisms.
► The experimental study on optimum switch FET devices for maximum power handling capability is presented.
► The 10-stacked SPDT switch is implemented in a 180-nm SOI CMOS process using optimized switch FET devices.
► The designed SPDT switch shows RF P1 dB greater than +40 dBm.