کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
746889 | 1462242 | 2013 | 8 صفحه PDF | دانلود رایگان |
This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20 ns) for the operating voltage of 1.0 V. The information is backed-up during POWER-DOWN/RESTORE cycle in two bipolar Oxide Resistive RAMs (OxRRAMs). The proposed NV-SRAM is designed with an 8T2R structure using 22 nm FDSOI technology and resistive memory devices based on HfO2. The stability and the reliability of the NV-SRAM cell is investigated by taking into account the variability of the transistors. It is shown that high ROFF/RON is necessary to ensure reliable RESTORE operation and high SRAM yield under cell area and power consumption constraints.
► We designed an NVSRAM cell with 22 nm FDSOI PDK for CMOS and HfO2 OxRRAMs.
► We showed that our NVSRAM cell is operational at high speed (20ns) and low voltage (1.5V).
► We presented the first analysis of VT variability on the stability of an 8T2R NV-SRAM.
► We showed that ROFF/RON of 10 is necessary to have sufficient reliability of RESTORE.
Journal: Solid-State Electronics - Volume 90, December 2013, Pages 99–106