Microcrystalline-Si thin-film transistors formed by using palladium silicided source/drain contact electrode

Microcrystalline-Si thin-film transistors (μC-Si TFTs) formed by using the source/drain contact electrode of self-aligned palladium silicide have been investigated. Both the self-aligned palladium silicided scheme and the previous top-gate staggered structure employ two-mask process steps for fabricating μC-Si TFTs. However, the self-aligned palladium silicided scheme would cause better device characteristics than the top-gate staggered structure, primarily due to more carrier tunneling. For a gate length of 2 μm, as compared to the top-gate staggered scheme, this silicided scheme can result in a 40% improvement of on-state current. In addition, as the gate length is reduced to 1 μm, considerable short-channel effect is caused for both the device schemes.