Formation of n-channel polycrystalline-Si thin-film transistors by dual source/drain implantation

Formation of n-channel poly-Si TFT devices by the dual source/drain (S/D) implantation scheme has been studied. By the dual-implantation scheme that performs both the high-energy/low-dose large-angle-tilt-implantation and the n+-S/D implantation in the same mask layer, lightly doped n−-region can be effectively formed without needing extra process steps and photo-mask layer in CMOS process integration. As a result, the off-state leakage current of the resultant TFT devices is significantly improved to be about two orders smaller than that for the conventional samples that just receives single n+-S/D implantation, attributable to lower electric field intensity near the drain region. However, by the dual-implantation scheme that employs high-energy/low-dose implantation with no tilt angle, namely as a conventional double-diffused drain scheme, the resultant device characteristics are just comparable to those caused by the conventional scheme.