A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs

A compact model of fringing field induced parasitic capacitance has been developed. Geometrical parameters such as gate length, gate electrode thickness, oxide thickness and spacer thickness have been considered. By using proper conformal mapping method, we analytically modeled the capacitance between gate electrode and source/drain including metal electrode filled in the contact holes. We compared the model with the results of 2-D device simulation, and found very good agreement.