Generic device abstractions for information processing technologies

Current CMOS devices operate at about six orders of magnitude above the kBTln 2 J/bit switching limit imposed by physics. Continued scaling of devices that are then densely packed and operated at attainable frequencies will result in the generation of thermal loads that cannot be managed by any known heat removal technology. Herein, we introduce an extension of the device energy barrier model to include extremely scaled interconnect systems. It is shown that the dissipation per device in interconnected circuits will considerably exceed isolated device dissipation, which is on the order of a few kBT. We next discuss possible successor/complementary logic devices that reduce the level of heat generation and we discuss new non-volatile memory techniques that could radically impact information processing architectures and hence the performance requirements for logic devices.