A novel area-efficiency multi-finger GGnMOS with high ESD robustness

• A novel multi-finger structure GGnMOS with an additional diode is proposed.
• The BV of the additional diode is designed as lower than the original device.
• The proposed structure device has 20% smaller area than the conventional one.
• The proposed device has the same second breakdown current as the conventional one.

For the multi-finger gate-grounded n-type MOS (GGnMOS) design, a large ballast resistance is generally needed to overcome the non-uniform turn-on problem under electrostatic discharge (ESD) condition. In this way, the total area is significantly increased. To overcome the disadvantage, a novel multi-finger GGnMOS structure with an additional low breakdown voltage diode is proposed in this paper. The experimental results show that, comparing with the conventional structure device, the proposed structure device requires much smaller ballast resistance to achieve uniform turn-on. As a result, the proposed structure reduces the total area by 20% and effectively improves the area-efficiency.