Pickup impact on high-voltage multifinger LDMOS–SCR with low trigger voltage and high failure current

• LDMOS–SCR with pickup has a higher concentration of PW, making higher capacitance.
• Higher parasitic capacitance in PW/NW diode junction makes the trigger voltage lower.
• HV LDMOS–SCR with pickup has lower trigger voltage and higher failure current.

The impact of inserting P+ pickup on high-voltage multi-finger laterally diffused metal–oxide–semiconductor–silicon-controlled rectifier (LDMOS–SCR) has been studied in this article. Four-finger LDMOS–SCR structures with finger length of 50 μm using 0.5 μm 18 V complementarily diffused metal oxide semiconductor (CDMOS) process were fabricated and tested. Theoretical analysis is carried out to make detailed comparisons between LDMOS–SCR with and without P+ pickup. It verifies that the multi-finger LDMOS–SCR with P+ pickup has greater electrostatic discharge (ESD) robustness and effectiveness. Furthermore, transmission line pulse (TLP) test has been done and the results show that the trigger voltage (Vt1) of the LDMOS–SCR with P+ pickup remarkably decreases from 46.19 to 35.39 V and the second breakdown current (It2) effectively increases from 8.13 to 10.08 A.