Calculating drain delay in high electron mobility transistors

• Derived drain delay (τDτD) expression in FETs with non-uniform velocity.
• For same depletion length (xm) & velocity profile (v[x  ]), τDτD> collector delay.
• For same xm & v[x  ], τDτD for FETs with field plates >τDτD for FETs without field plates.
• For constant velocity (vsat), τD=xm/(αvsat)τD=xm/(αvsat).
• Derived α in terms of weighting function and in terms of image charges.

An expression for the signal delay (drain delay) associated with electrons traveling through the gate–drain depletion region has been obtained for nonuniform electron velocity. Due to the presence of the gate metal, the signal delay through the gate–drain depletion region was shown to be larger than the signal delay in the base–collector depletion region of a bipolar transistor when equal depletion lengths and velocity profiles were assumed. Drain delay is also shown to be larger in transistors with field plates (independent of field plate connection) compared to transistors without field plates when equal depletion lengths and velocity profiles were assumed. For the case of constant velocity, two expressions for the proportionality constant relating drain delay and electron transit time across the depletion were obtained.