Facet engineering for SiGe/Si stressors in advanced CMOS technology

A two-layer SiGe stressor was introduced for our CMOS technology containing a bottom layer with high Ge content to induce more stress to the channel and a top layer with lower Ge content for better nickel silicidation. However, even with the top lower Ge layer, defects were found after silicidation causing contact punch through. Since it is well known that the silicidation improves for Si, the SiGe top layer was replaced by a Si layer (Si-cap). Evaluation on 750 °C and 850 °C grown Si-cap was done. Different temperature grown Si-caps showed different growth behavior with morphology of the Si-cap grown at 850 °C completely different than that of the Si cap grown at 750 °C. There was a clear {3 1 1} facet formation for the higher temperature Si-cap resulting in a pinning effect to the spacer edge similar to that observed for the SiGe-cap. The faceted Si-cap improved silicidation and device parameters enabling the extension of this integration approach for SiGe/Si stressors to the more advanced technology nodes.