Behavior of the parameters of microcrystalline silicon TFTs under mechanical strain

• N and P microcrystalline silicon top-gate TFTs processed on PEN at maximum 180 °C.
• Symmetric N and P microcrystalline silicon top-gate TFTs.
• Behavior of mobility and threshold voltage under tensile and compressive bending.
• Mechanical behavior similar to cSi strained MOSFETs in nano-scale technologies.
• Similarity explained from the behavior of the μc-Si active layer.

N-type and P-type microcrystalline silicon top-gate TFTs, processed directly on PEN plastic substrate at maximum temperature of 180 °C, were mechanically stressed.These TFTs were bent by different curvature radii varying between infinite (flat) and 0.5 cm. The tensile stress increases the electron mobility and the compressive stress decreases it. The tensile stress decreases the threshold voltage of N-type TFTs while the compressive stress increases it. These trends are inversed if the type of stress changes OR the type of TFTs changes.The total behavior under mechanical stress is exactly similar to that of single crystalline silicon MOSFETs in nano-scale technologies (90, 65, 45, 32 nm), where nano-scale stress is introduced in the goal to engineer the electrical parameters. The similarity originates from the microcrystalline silicon active layer that behaves like single crystalline silicon even if the stress effects are softened by the grain boundaries and the multiple crystalline orientations of the grains.