A novel model of the high-voltage VDMOS for the circuit simulation

• A novel model of the VDMOS for the circuit simulation is presented.
• The accumulation region is modeled based on the surface potential calculation.
• The pinch-off effect of the parasitic JFET region is considered in the modeling.
• The three important capacitances, Cgd, Cds and Cgs, have been modeled.
• The model accurately describes the characteristics of the target VDMOS.

A novel model of the high-voltage vertical double diffused MOS (VDMOS) for the circuit simulation has been presented in this paper. In the DC section of the model, the VDMOS is treated as a normal MOS device with four series resistors. In contrast to other VDMOS models, the resistance model of the accumulation region is built based on the surface potential calculation method. Moreover, both the channel depletion and the pinch-off effects of the parasitic JFET region are also taken into account carefully. In addition, the three important capacitances, Cgd, Cgs and Cds, have been considered and modeled in the AC section. The proposed complete device model is validated by the comparison with the measured data of the target VDMOS. The comparison results demonstrate that the new model gives the accurate descriptions for both DC and AC characteristics of the VDMOS device.