کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
747822 | 1462251 | 2013 | 6 صفحه PDF | دانلود رایگان |
A high SET/RESET speed phase change memory cell with a NMOS selector is achieved by optimizing cell structure, material, programming circuit and testing method. An asymmetric T-shape cell structure increases the current density in the programmable region and reduces thermal diffusion in the cell. Super-lattice phase change material has a lower thermal conductivity. The circuit has a fast response and reduces the falling time of RESET pulse to 0.9 ns which enables a fast phase change operation of the memory cell. The testing system has good signal integrity and transmits the undistorted ultrafast programming enable signal to I/O ports of the chip. The optimized SET time is 50 ns and RESET time is 2 ns.
► A high SET/RESET speed phase change memory cell with a NMOS selector is achieved by optimizing cell structure, material, programming circuit and testing method.
► An asymmetric T-shape cell structure increases the current density in the programmable region and reduces thermal diffusion in the cell.
► Super-lattice phase change material has a lower thermal conductivity.
► The circuit has a fast response and reduces the falling time of RESET pulse to 0.9 ns which enables a fast phase change operation of the memory cell.
► The testing system has good signal integrity and transmits the undistorted ultrafast programming enable signal to I/O ports of the chip. The optimized SET time is 50 ns and RESET time is 2 ns.
Journal: Solid-State Electronics - Volume 81, March 2013, Pages 157–162