Modeling the impact of substrate depletion in FDSOI MOSFETs

• Substrate depletion in FDSOI transistor is studied for different ground planes.
• BSIMIMG model is verified on both NMOS and PMOS FET.
• Model shows excellent geometrical and temperature scaling.
• Substrate depletion effect is modeled accurately using proposed model.

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C–V and I–V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50 nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.