Evaluating the CDM-Robustness of the input buffer with very fast transmission line pulse

• In previous studies, it is difficult to correlate VFTLP results with CDM results.
• In this paper, evaluating CDM-Robustness of the input buffer using VFTLP is proposed.
• The dynamic-characteristic impedance of the ESD device under VFTLP test can be obtained.
• The dynamic-characteristic impedance provides a way to evaluate CDM threshold voltage.
• In this work, the estimated CDM passing level can closely match the CDM test result.

In this paper, a scheme for how to utilize VFTLP (very fast transmission line pulse) data to design an input buffer circuit for CDM (charged-device model) ESD protection is reported. The impedance of the ESD device under VFTLP stress is nearly 120 Ω at the beginning of turn-on transient, and decreases with time toward 10 Ω prior to the voltage falling below 0 V. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit.