A new compact analytical model of single electron transistor for hybrid SET–MOS circuits

• A compact analytical model of SET suitable for hybrid SET–MOS circuit is proposed.
• Eleven island states are considered in the model to accommodate large values of Vds.
• Device characteristics of the model are in good agreement with the SIMON results.
• SET–MOS hybrid inverter and NAND gates are simulated and verified with SIMON results.
• The proposed model can be implemented in a commercial simulator such as SPICE.

A new compact analytical model of single electron transistor suitable for circuit simulation of hybrid SET–MOS is proposed, which is developed on the basis of the Orthodox theory of single electron tunneling using master equation. Eleven island states are considered in the proposed model, which is valid for single or multi-gate symmetric/asymmetric SET. Since the model considered a large number of states, it is valid for a large range of drain to source voltage thereby making it suitable for hybrid SET–MOS circuit application. The device characteristics produced by the proposed model are verified with the Monte Carlo based simulator SIMON and good agreement is observed. The effects of the operating temperature on the accuracy of the device characteristics are thoroughly investigated. Since the proposed model is developed following a computer aided design framework, it can be implemented in any popular commercial circuit simulator such as SPICE to provide a promising environment for designing SET–MOS hybrid circuits. Finally a SET–MOS hybrid inverter and a NAND gate are simulated and verified with SIMON results to prove the accuracy of the model.