Cell libraries for robust low-voltage operation in nanometer technologies

The key challenge of wireless sensor nodes is their total power dissipation, hampering their autonomous operation due to limited battery life time. Aggressive voltage scaling reduces both dynamic and leakage power, prolonging the battery life time. The challenges of aggressive voltage scaling into the subthreshold region includes the pronounced effect of process variability and the significantly reduced performance. In this paper, these challenges are addressed by first devising a novel cell library pruning methodology to ensure reliable voltage scaling based on the noise margin criterion. Using the proposed approach, further voltage scaling is possible, enabling more than 20% energy savings as compared to the classic approach of avoiding high fan-in cells and/or complex gates. Then, the design of standard cells for two dedicated design points is presented which considers both the transistor geometry (L, W, and the number of fingers) as well as the cell layout to achieve up to a 3× speed-up as compared to a conventional methodology. The result is also validated in measurement leading to the comparison of a datapath module of slightly better energy efficiency and 3× better performance.

► We optimize standard cell libraries for lower energy consumption and reliable operation.
► Our novel pruning methodology achieves more than 20% energy savings.
► Additional standard cell design points are derived for better performance.
► This is combined with noise margin analysis.
► Silicon measurements confirm an up to 3.5× speed-up with better reliability.