کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
748040 | 1462230 | 2014 | 5 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs](/preview/png/748040.png)
The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications.
Journal: Solid-State Electronics - Volume 102, December 2014, Pages 93–97