Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

• Impact of UTBOX with GP and local Vb on bitcells performance improvement.
• The VT variation increases when opposite GP doping is used for NMOS and PMOS.
• As the BOX thickness is reduced this VT variation versus Vb increases.
• Back bias improve bitcells performance in FBB and RBB as in bulk.
• For gated and STI diodes, hybrid technology improves TLP at the same level as bulk.

In this paper, we study how to boost the performance of FDSOI (Fully-Depleted Silicon On Insulator) devices with High-K and Single Metal gate by using the combination of Ultra-Thin Buried Oxide (UTBOX), Ground Plane (GP) and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of threshold voltage VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology.