Surface potential compact model for embedded flash devices oriented to IC memory design

• A surface potential-based model for embedded flash memory cells is proposed to enable device performance optimization.
• The model includes charge balance effects on the isolated floating gate node, parasitic couplings between the cell terminals.
• The model has been validated on a large set of hardware measurements and TCAD simulations in DC, AC and transient analyses.

A surface potential-based model for embedded flash memory cells has been developed with the purpose of providing a comprehensive physical understanding of the device operation suitable for performance optimization in memory circuit design. The device equations account for charge balance effects on the isolated floating gate node and parasitic couplings between the terminals of the memory cell. The compact model supports DC, AC and transient analyses, including program/erase bias scalability, drain disturb and memory endurance degradation due to oxide aging. After validation, the model has been applied to parametric analysis and used to evaluate critical trade-offs in memory design.