Improvement of metal gate/high-k dielectric CMOSFETs characteristics by atomic layer etching of high-k gate dielectric

Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the improvement of the off-state leakage current (Ioff), which was mainly attributed to the decreased perimeter component of the gate leakage current (IG) particularly, at the low field region. The better electrical characteristics are due to the low trap density at the edge of gate oxides in the S/D region of CMOSFETs.

► Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in CMOSFETs.
► Its electrical characteristics were compared with those etched by wet or reactive ion etching.
► The CMOSFET etched by the ALE showed the improvement of Ioff.
► It was mainly attributed to the decreased perimeter component of IG.
► The results are due to the low trap density at the edge of gate dielectric in the S/D region.