Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Trap densities (Dt) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance–voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. Dt in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that Dt is very roughly 1018 cm−3 eV−1 near the midgap and becomes tail states near the conduction and valence bands. As a result, Dt is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of Dt on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing.

Low-frequency (low-f) capacitance–voltage (C–V) characteristics with a variation of the process conditions of the post annealing. Trap density (Dt) as a function of the energy level (E) with a variation of the process conditions of the post annealing.Figure optionsDownload as PowerPoint slideHighlights
► Dt in entire bandgaps of SPC–TFTs is extracted by measuring low-fC–V characteristics.
► Dt in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs.
► Dt is roughly 1018 cm−3 eV−1 near the midgap and becomes tail states near Ec and Ev.
► Dt is distributed like U shape in the bandgap, but humps appear around the midgap.
► The hump can be reduced by increasing annealing temperature and time.