کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
748392 894758 2008 6 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
An ultra-low power CMOS random number generator
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
An ultra-low power CMOS random number generator
چکیده انگلیسی

This paper proposes an ultra-low power CMOS random number generator (RNG), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 μm CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 μW. This novel circuit is a promising unit for low power system and communication applications.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 52, Issue 2, February 2008, Pages 233–238
نویسندگان
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