Wafer scale thin-film transistors using different semiconducting purity nanotubes, dielectric materials and gate control

Wafer scale fabrication and characterization of thin-film transistors (TFTs) using 90% and 95% purity of semiconducting single walled carbon nanotubes (s-SWCNTs), with SiO2 and HfOx gate oxide materials and having different gate structure are reported in this paper. The semiconducting nanotube TFTs (SN-TFTs) with high-k dielectric gate oxide (HfOX) have exhibited lower threshold voltage, steeper sub-threshold slope, large on-current and higher transconductance compared to SiO2 based devices of identical channel dimensions. Due to the higher metallic nanotube content SN-TFTs with 90% pure s-SWCNTs have exhibited lower on–off current ratio, but have shown large current density (on-current/channel width) compared to identical dimension devices with 95% s-SWCNTs fabricated under similar process conditions. Several SN-TFTs having different channel dimensions with capability to control each devices independently are fabricated on the same wafer. The local gate SN-TFTs have outperformed the devices with global gate structure in terms of threshold voltage, sub-threshold swing, current density and carrier mobility. These local gate SN-TFTs have exhibited a sub-threshold slope of 400 mV/decade, a maximum current density of 6.1 μA/μm and a maximum carrier mobility of 56 cm2/V s.

► 90% and 95% pure s-SWCNTs fabricated under same process is not studied.
► HfOX and SiO2 SN-TFTs fabricated under same process is not studied.
► Local back-gate structure at wafer scale is not studied.