Physical mechanism of interpoly capacitance reduction in high-voltage stress

Interpoly capacitors show degradation in form of capacitance reduction in the whole range of CV characteristics when subjected to high-bias DC or alternating stress. When using these capacitors in oscillator circuits, shift in the resonant frequency may occur, leading to IC performance failure. Significant capacitor degradation occurs at biases that are much lower than the breakdown voltage BV (already at ∼50% BV), and bellow Qdb limit of interpoly dielectric. Degradation is strongly enhanced with reduction in the interpoly dielectric thickness (ONO or oxinitride). We propose a physical mechanism that completely explains the degradation, which involves electron tunneling injection, trapping in the dielectric and simultaneous poly-depletion of both electrodes. Assuming this model, analytically computed CV curves fully reflect all qualitative features observed in experimental degradation characteristics, and enable quantitative fitting of them. This degradation effect sets reliability limit for decrease in interpoly dielectric thickness in capacitors used in RF ICs, where they are subjected to large voltage excursions.

► For thin dielectric, interpoly capacitance value may decrease in high-bias stress.
► Shift in resonant frequency that occurs leads to failure of specific RF IC.
► Degrading bias is much lower than BDV, and bellow Qdb of interpoly dielectric.
► Electron injection, trapping and poly-electrode depletion explain the effect fully.
► Effect sets reliability limit for interpoly dielectric thinning in an RF IC class.