Operational upsets and critical new bit errors in CMOS digital inverters due to high power pulsed electromagnetic interference

The effects of high power pulsed electromagnetic interference from high power microwave sources on static and dynamic operation of CMOS digital inverters, is reported. The output voltage and current transfer characteristics of 1.5 μm and 0.5 μm CMOS inverters were measured under pulsed interference at frequencies of 1 GHz and 3 GHz. New bit-flip errors have been identified to occur at or below the threshold voltage of the n-channel MOSFETs in the first stage of the inverters, resulting in propagating errors. Errors were also observed for above threshold, which propagated in subsequent stages either as noise or as bit-flip errors when exceeding the device noise margins. Time domain measurements showed that bit-flip error rate increased with peak power for the same average power. The current transfer characteristics showed significantly increased inverter output currents at the ON, switching, and OFF states with higher peak power. It is shown that peak power is one of the critical parameters for the increased threat level of pulsed interference.