Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations

Previously, we reported current–voltage characteristics of silicon nanowire junctionless transistors with a 3 nm gate length and a 1 nm wire diameter as calculated within a Density Functional Theory (DFT) framework. Our results reveal that a 3 nm gate length can provide good electrostatic control over the channel. In this work, sensitivity to dopant position within the nanowire cross section on the band structure is explored. Our calculation of the current–voltage characteristics is extended here by considering the role of charge self-consistency on the charge carrier transport, and in particular the subthreshold slope in these nanowire transistors is examined. Even at such small length scales, the self-consistent calculations indicate that subthreshold slopes of 74 and 80 mV/dec can be obtained for p-channel and n-channel devices, respectively.

► A 3 nm gate length can provide good electrostatic control over the channel.
► Sensitivity to dopant position within the nanowire cross section on the band structure is explored.
► Subthreshold slopes of 74 and 80 mV/dec can be obtained for p-channel and n-channel devices, respectively.
► First principles calculations indicate that the dopant atoms are energetically more favorable on surface sites.