A model for the C–V characteristics of the metal–ferroelectric–insulator–semiconductor structure

A model is developed to describe the characteristics of the metal–ferroelectric–insulator–semiconductor (MFIS) structure based on the dipole switching theory (DST) and the silicon physics of metal–oxide–semiconductor (MOS) structure. The ferroelectric dipole distribution function is used to simulate the history-dependent electric field effect of the ferroelectric layer. Using the model, the thickness effects of the ferroelectric and insulator layers on the capacitance–voltage (C–V) characteristic and the memory window were investigated for Pt/SBT/ZrO2/Si and Pt/BLT/MgO/Si structures. All the simulation results show good agreement with the experimental results, indicating that the model is suitable for simulating the C–V characteristic and the memory window of MFIS structure. In addition, the mathematical description is simple and can be easily integrated into the electronic design automation (EDA) software for circuit simulation.