کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
748996 | 894801 | 2008 | 9 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack](/preview/png/748996.png)
This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy2O3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (JG) reduction; (2) adding a cap has no significant impact on Tinv(<1 Å), while up to ∼5 and 2 Å reduction occurs for SiON and HfSiON Yb-implanted devices, respectively, (3) the largest JG reduction (150×) is obtained for capped SiON devices due to dielectric intermixing and formation of a new high-k dielectric (DySiON), comparable to HfSiON in JG and mobility but with 500 mV smaller VT; (4) on the other hand, being less invasive to the host dielectric, the optimized Yb I/I option gives 18% improved mobility compared to capped SiON devices; (5) excellent process control and reliability behavior (VT instability by a.c. pulsed IV, PBTI and TDDB) is reported for both eWF tuning methods. They allow ΔeWF(n−p) values up to ∼800 meV when combined with Ni–silicide FUSI phase engineering, promising for low-VT CMOS.
Journal: Solid-State Electronics - Volume 52, Issue 9, September 2008, Pages 1303–1311