Hole transport in DGSOI devices: Orientation and silicon thickness effects

We simulate double-gate SOI p-channel devices using different surface and channel orientations, by solving self-consistently the 6-band k·pk·p and Poisson equations. Electrostatic properties such as inversion charge concentration and its spatial distribution are computed, analyzing the effects of silicon layer thickness and surface orientation. Hole mobility is also computed employing Kubo–Greenwood formula. Mobility improvement previously found in bulk p-MOSFETs for substrate orientations different from (0 0 1) is also observed for SOI devices, and such improvement grows for decreasing silicon layer thickness. Population of the first hole subband, its conduction effective mass and phonon scattering form factor are studied as a function of orientation and channel thickness to have an insight into mobility results.