Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion

In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.