Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing

We report the simultaneous improvement of both on- and off-properties for n- and p-channel MOSFETs by means of carbon co-implantation at extension level, using conventional spike annealing. For the first time, spike-annealed NFETs with phosphorus-implanted source/drain extensions (SDE) are shown to outperform conventional As-implanted devices in the deca-nanometric range. Parameters such as on-current, drain-induced barrier lowering (DIBL), external resistance (REXT) vs. effective channel length (Leff) trade-off are examined. To obtain the full benefit of carbon co-implantation, we recommend adjusting pocket, highly doped drain (HDD) and spacer parameters.