Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process

A strained Si1−xGex-channel PMOSFET, fully integrable in a standard Si1−xGex BiCMOS process is proposed. It uses an n+-polysilicon emitter of the bipolar transistor as the gate, and has a p-type Si1−xGex channel, making it a truly buried channel device. It uses only two extra masks and a few minor changes in the baseline BiCMOS flow, keeping the additional processing cost low. The basic device design is systematically optimized to get the best compromise among hole confinement in Si1−xGex, layer stability and channel hole mobility. Optimization was done using Ge fraction dependent process and device simulation parameters for the first time. A novel, semi-analytical approach to model the effect of Ge fraction on hole current was used. The impacts of Si cap layer thickness, Si1−xGex film thickness, channel doping and Ge fraction were investigated. During process and device design, care was taken to ensure that the Si1−xGex layer remains strained as well as the standard available devices are not impacted by additional process steps. The optimized device shows a 2× gain in transconductance and in drain current over the standard PMOS device available in the baseline process.