Calculation of the phonon-limited mobility in silicon Gate All-Around MOSFETs

The continuous reduction of device dimensions and the design of new silicon-on-insulator (SOI) structures which confine the carriers in two dimensions (2D) have a considerable influence on electron transport properties. The aim of this work is to study the phonon-limited electron mobility in silicon nanowires where the carriers are confined in 2D and we are dealing with a 1D electron gas. It has been found that for devices with silicon cross-sections below 10 nm, the overlap factor rapidly increases, producing a notable degradation of the phonon-limited mobility.