Impact of device scaling on the 1/f noise performance of deep submicrometer thin gate oxide CMOS devices

This paper presents the effects of technology and geometry scaling on the 1/f noise performance of deep submicrometer transistors taken from four advanced CMOS technologies, namely the 0.13 μm, 0.18 μm, 0.25 μm and 0.35 μm nodes. For the 0.13 μm technology node, three different process flavours consisting of the generic (G) process flow, the low voltage/high performance (LV/HP) process flow and the low standby power (LSP) process flow have been investigated. The higher degree of gate dielectric nitridation with technology downscaling from 0.35 μm node to 0.13 μm G node has resulted in a severe degradation of the 1/f noise performance of the transistors by approximately three orders of magnitude. On the contrary, the employment of 0.13 μm LSP transistors have been demonstrated to lower the 1/f noise spectra by approximately two orders of magnitude as compared to the 0.13 μm LV/HP transistors, which gives the worst 1/f noise performance among the three different process flavours in the 0.13 μm node. The study of device geometry scaling on 0.13 μm LSP transistors shows that in general the scaling trend follows the SId∝WL3 rule, where SId, W and L represent the current noise spectral density, the active gate width and length of the transistor, respectively. For devices with gate area <1 μm2, a large dispersion in the 1/f noise level can be seen. This phenomenon has been correlated to the existence of Lorentzian-like spectra for small area transistors. The investigation of the effect of scaling the transistor’s aspect ratio (W/L  ) reveals a (SId×WL)∝WL2 dependence.