Influence of different deposition conditions of top and bottom electrode on the reliability of Sr0.8Bi2.2Ta2O9 ferroelectric capacitors

In this study, the reliability (fatigue, imprint, and retention) of Pt/SBT/Pt capacitors was investigated. For non-integrated test capacitors, using a different process for top and bottom electrode formation, fatigue degradation is larger than for integrated capacitors using symmetric top and bottom electrode deposition process. Also, for the non-integrated capacitors, imprint behavior and retention loss were observed to depend on the voltage polarity. From hysteresis as well as leakage characteristics, these effects were attributed to the presence of a built-in field favoring the polarization of SBT from the bottom to the top electrode in non-integrated capacitors. The built-in field was attributed to defect generation during the top electrode sputtering at room temperature. For the integrated capacitors, whereby the top electrode is deposited using the same high temperature process (>150 °C) as the bottom electrode, neither imprint degradation nor retention loss was observed under the applied conditions, showing excellent reliability of integrated SBT capacitors.