An improved junction capacitance model for junction field-effect transistors

A new junction capacitance model for the four-terminal junction field-effect transistor (JFET) is presented. With a single expression, the model, which is valid for different temperatures and a wide range of bias conditions, describes correctly the JFET junction capacitance behavior and capacitance drop-off phenomenon. The model has been verified using experimental data measured at Texas Instruments.