Fabrication of poly-Si TFT with silicided Schottky barrier source/drain, high-κ gate dielectric and metal gate

In this paper, a polycrystalline Si thin film transistor (TFT) with self-aligned silicide Schottky barrier source/drain (SSD), high-κ gate dielectric and metal gate electrode is demonstrated using a simplified low temperature process. After crystallization of α-Si, the thermal budget for device fabrication is reduced to ∼420 °C due to elimination of the implant doping and subsequent activation annealing procedures. P-channel SSD-TFT with PtSi S/D shows an acceptable electrical performance with Ion of 1.5 μA/μm for the Lg = 2.5 μm device at Vgs = Vds = −5 V and Ion/Ioff ratio of ∼104. However, Ion of the n-channel SSD-TFT with DySi2−x S/D is about two orders of magnitude smaller due to the relatively high Schottky barrier height and poor silicide quality of the DySi2−x/poly-Si contact.