Electrical characteristics and optimization of extended-drain MOS transistor with dual-workfunction-gate for mixed-signal applications

• The extended-drain MOS transistors with dual-workfunction-gate were fabricated.
• A qualified 0.18-μm 20-V class HV CMOS process was applied for fabrication.
• The fabricated devices were investigated for mixed-signal applications.
• The p+ and n+ gate length ratio is major factor for device optimization.
• The p+ and n+ gate length ratio can be another design parameter.

This paper presents the electrical characteristics of high-voltage (HV) extended-drain MOS (EDMOS) field-effect transistor with dual-workfunction-gate (DWFG) to enhance the device performance and device optimization for mixed-signal applications. For n-channel DWFG EDMOS device fabrication, the polycrystalline-silicon (poly-Si) gate on the source and drain side were doped by p+ and n+ ion implantation, respectively. The DWFG device with shorter p+ poly-Si gate length showed lower on-resistance (RON) characteristics compared to the conventional device. Therefore, the DWFG device with shorter p+ poly-Si gate length is suitable for switching applications. On the other hand, the best improvements in the drain conductance (gds) and intrinsic voltage gain (AV), which is important parameters of analog circuits, were shown in the DWFG device with identical n+ and p+ poly-Si gate length.