Preliminary results on low power sigmoid neuron transistor response in 28 nm high-k metal gate Fully Depleted SOI technology

• Preliminary formal neuron device in FDSOI 28 nm high-k metal gate is introduced.
• We report a sigmoid IV response compared to standard one.
• Ultra low leakage is also addressed is this solution: 10,000 times less at least.

The purpose of this paper is to describe a preliminary approach to achieve a sigmoid neuron transistor response using the 28 nm high-k metal gate Fully Depleted SOI (FDSOI) technology. It is well known that a neural network is an ambitious way to handle signal and/or data flow. Of interest also is the ‘learning phase’ of the proposed structure. However, the major difficulty of such structures, where the elementary device is a “Neuron Design (ND)” is in their integration. The elementary ND is based upon a circuit with at least ten interconnected CMOS transistors in order to obtain a sigmoid response activation function (in this example) with multiple inputs typically as per the McCulloch and Pitts model. Given that a large number of NDs are required to build an Artificial Neural Network (ANN), the power consumption of such a structure is a key topic that is also addressed. Another open question concerns the dispersion response due to process variability. This study reports on a new single undoped Formal Neuron Transistor (NT) solution.